Imperas Virtual Platform Solutions at ARM TechCon Oct 2017

Imperas Accelerates Software Development, Debug and Test for ARM-Based Embedded Systems; Participates in Software Security Panel

Imperas Software Ltd. will exhibit at the 2017 ARM TechCon and also participate in an embedded software panel discussion focused on security: “Hypervisors:  A Real Trend in Embedded, or Just Hype?

Imperas invites attendees to register for a demonstration of Imperas embedded software development, debug and test solutions for ARM-based systems.

Demo Highlights:

  • Solutions for custom/proprietary processor modeling, early software development and comprehensive software testing.  Use cases include porting and bring-up of operating systems and validation of secure software and architectures. See advanced software analysis with Imperas OS-aware verification, analysis and profiling (VAP) tools, code coverage capabilities, memory monitoring, and fault simulation.
  • Open Virtual Platforms (OVP) models and platforms for the full line of ARM processors, including Cortex-A, R and M families, ARM big.LITTLE architecture and multi-cluster ARMv8 architectures. See Linux booting on various Cortex-A platforms and RTOS booting on Cortex-M platforms.

Panel: Hypervisors:  A Real Trend in Embedded, or Just Hype?

  • Abstract: Security and functional safety are two key elements of embedded system development, and increasingly system architects are looking at solutions at the point where software touches the hardware.  Processor architecture changes such as hardware virtualization extensions and TrustZone, and software changes in hypervisors and real time operating systems (RTOSs) take advantage of these architectural features.  What are the real differences in these hardware and software technical innovations?  For processors, how do hardware virtualization extensions compare with TrustZone for use for security and safety?  For resource management, safety and security, how do new hypervisor offerings stack up to the established technology of RTOS?  Are hypervisors a real trend in embedded systems or just hype?  
  • Moderator: Brian Bailey of Semiconductor Engineering. 
  • Participants:
    • Chris Turner, ARM, product marketing manager for Cortex-R family processors;
    • Simon Davidmann, Imperas Software, founder and CEO;
    • Cesare Garlati, prpl Foundation, chief security officer;
    • Jack Greenbaum, Green Hills Software, director of engineering, advanced products.

When: Conference: October 24-26, 2017. Expo: October 25 and 26, 2017.  

When: Panel session:  Wednesday, October 25, 10:30am – 11:20am.

Where: Santa Clara Convention Center, Santa Clara, CA. Imperas booth is #421 in the exhibition area.

For more information, or to set up meetings with Imperas at ARM TechCon, please email sales@imperas.com.

ARM TechCon 2017 provides high level keynotes, detailed technical presentations and ARM ecosystem exhibits, all aimed at advancing industry discussions of state of the art solutions to embedded systems issues.

RISC-V Paper by Imperas at 15th International System-on-Chip SoC Conference Oct 2017

Imperas Presenting on Accelerated Software Development, Debug and Test for RISC-V Platforms

Imperas Software Ltd. will participate in the 15th International System-on-Chip (SoC) Conference, presenting a paper: “RISC-V Models and Simulation Enable Early Software Bring Up.”

The 15th International System-on-Chip (SoC) Conference will be held October 18 – 19, 2017 at the University of California, Irvine (UCI) – Calit2.  The theme for this years conference is “Secure and Intelligent Silicon Systems for Emerging Applications.”

Paper: RISC-V Models and Simulation Enable Early Software Bring Up

  • As RISC-V processor cores start to be designed into new SoCs, software requirements need to be considered.  One of the issues with moving to RISC-V based SoCs is porting operating systems, drivers, firmware and applications from existing platforms.  Can this be easily accomplished?  Can it be accomplished, in the majority, before silicon is available?  Virtual platforms, or software simulation, can help accelerate this porting and bring up process.  Virtual platforms provide a near real time software simulation environment for executing the actual software binaries, plus have full debug, analysis and test tools. 
  • Now there are not only models of RISC-V processor cores – generic RISC-V, SiFive, Andes; 32 and 64 bit cores – but also models of platforms running operating systems.  These Extendable Platform Kits (EPKs) enable software engineers to quickly get started, months before any hardware, even FPGA prototypes, are available.  For example, there is an EPK available of a Microsemi platform, using a SiFive E31 RV32-based core, running FreeRTOS. 
  • Virtual platform environments also enable the use of debug, analysis and test tools, not only for RISC-V, but in the case of a heterogeneous platform, supporting the multiple processors on the platform.  Also, as Agile methods, including Continuous Integration Continuous Test (CICT) are adopted by embedded software teams, virtual platforms with their ease of automation enable this technology to be implemented.
  • This paper provides a summary of the RISC-V processor models available through the Open Virtual Platforms (OVP) website (www.OVPworld.org), shows a demo of the Imperas Microsemi E31/FreeRTOS EPK, and discusses the use of virtual platforms in accelerating migration to RISC-V based SoCs and improving software quality. 

When: Exhibit and workshops, October 18 – 19, 2017.

Where: University of California, Irvine, 4100 Calit2 Bldg. #325, Irvine, CA 92697.

To set up meetings with Imperas, please email sales@imperas.com.

For more information on the 15th International System-on-Chip (SoC) Conference, see http://www.socconference.com.